The present invention relates to dynamic random access memories (DRAMs). More specifically, the invention relates to a differential sensing method and apparatus for DRAMs.
RAM devices have become widely accepted in the semiconductor industry. Furthermore, system-on-chip (SOC) devices typically include internal RAM for storage of information such as instructions and/or data. Internal memory blocks in an SOC device typically occupy substantial chip area of an integrated circuit (IC) chip that contains the SOC device. For example, internal memory blocks may occupy as much as about 70% of the IC chip area of an SOC device. The configuration of internal memory in SOC devices are generally similar to the configuration of memory in individual memory chips.
Each block of RAM includes a number of memory cells. Each memory cell typically stores one bit of information. Typical RAM blocks have capacity to store anywhere from thousands to millions of bits of data. Since vast numbers of memory cells are used to store information in RAM blocks, the size of RAM blocks depends, to large extent, on the size of each memory cell.
Memory cells in dynamic random access memory (DRAM) blocks typically require less number of transistors per bit than cells in a static random access memory (SRAM). For example, some DRAM blocks contain memory cells with three transistor (3-T) per bit, while other DRAM blocks contain memory cells with one transistor (1-T) per bit. Therefore, DRAM blocks of SOC devices and DRAM chips are typically smaller than SRAM blocks with similar information storage capacity.
However, unlike the differential SRAM cell structure that lends itself to differential sensing implementation, a single ended DRAM cell structure does not normally lend itself to differential sensing implementation. Differential sensing is the preferred sensing method due to its noise immunity, robustness and speed.
Therefore, there is a need for a DRAM structure that takes less area, but is capable of an advantageous differential sensing that is less prone to process and temperature variations.
Present invention describes a new design and architectural arrangement that allows for efficient implementation of differential sensing in single ended DRAM arrays. According to one embodiment of the present invention, a respective local sense amplifier compares the accessed memory cell data with a dummy cell data in the opposite or adjacent column of an accessed block, amplifies the result of the comparison and puts the data on a global bit line. In one embodiment, the invention is process and temperature invariant using reference method and means for canceling cross coupling between read lines and write lines. In one embodiment, a relative simple 4-transistor sense amplifier is augmented with two PMOS transistors to provide a fast and efficient sense amplifier that limits the voltage swing in the respective global bit lines for both read and write cycles. Additionally, a single transistor current sink, as part of the sense amplifier, provides layout flexibility and scalability and better voltage swing and speed.
In one aspect, the present invention discloses a DRAM with differential sensing means comprising: a top block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective top bit line; a bottom block of data cells including a plurality of data cell subsets, wherein each of the data cell subsets is coupled to a respective bottom bit line; a plurality of sense amplifiers positioned between the top block of data cells and the bottom block of data cells, each sense amplifier of the plurality of sense amplifiers is shared by a respective top bit line and a respective bottom bit line; a first replica memory cell with a portion of driving capability of a data cell, wherein the first replica memory cell turns on coupling a respective sense amplifier to a respective bottom bit line when a data cell in the top block of data cells is accessed; and a second replica memory cell with a portion of driving capability of a data cell, wherein the second replica memory cell turns on coupling a respective sense amplifier to a respective top bit line when a data cell in the bottom block of data cells is accessed.
In another aspect the present invention describes a method for differential sensing of a hierarchical DRAM. The DRAM includes a first block of data cells comprising a plurality of data cell arrays, and a second block of data cells comprising a plurality of data cell arrays, each of the data cell arrays includes a plurality of data cells, and a sense amplifier array positioned between the first block of data cells and the second block of data cells, each sense amplifier in the sense amplifier array shared by a respective data cell array in the first block and a respective data cell array in the second block. The method comprising the steps of: activating a first replica memory cell with a portion of driving capability of a data cell for connecting a respective sense amplifier to a respective data cell array in the second block when a data cell in the first block of data cells is accessed; and turning on a second replica memory cell with a portion of driving capability of a data cell for connecting a respective sense amplifier to a respective data cell array in the first block when a data cell in the second block of data cells is accessed.